1. Field of the Invention
The invention relates generally to workload analysis, and more particularly, to systems and methods for providing software application-level workload analysis of simulated hardware systems.
2. Description of the Related Art
The design of future microprocessors and system architectures etc. relies heavily on an ability to reliably evaluate and analyze the workload performance for proposed microprocessors and system architectures before they are built. Although significant work has been done to analyze and profile workload performance through software code inspection and measurement on existing hardware systems, such work is primarily focused on correlating the resulting workload performance data to software application performance on the existing hardware systems and on extrapolating the performance data obtained from the existing hardware systems to anticipate the performance of future hardware systems. On the other hand, little work has been done to facilitate software analysis in performance simulation environments for emerging microprocessors and system architectures etc. not yet built. For example, currently it is difficult to identify the software application functions responsible for most of the TLB (Translation Look-aside Buffer) misses for a simulated hardware system or to relate software application memory segments to cache interface patterns.
This inability to adequately perform application-level analysis of emerging hardware simulations is also due, in part, to the segregation of application performance expertise and hardware simulation expertise in system architecture design environments. More particularly, the tools that are used to facilitate performance workload analysis and the tools that are used to facilitate hardware simulation are typically used in isolation, resulting in a technical barrier to opportunities to cross-leverage knowledge. For instance, there are many tools to analyze workload instruction traces, but none which offer the flexibility to run dynamically without modification in the multiple stages of a trace-driven or execution-driven etc. hardware performance simulation of emerging architectures. Consequently, architects are often provided with workload analysis data that is specific to current hardware systems and the architects are left to extrapolate this workload analysis data obtained from a current hardware system to design a future, emerging, or new hardware system, a process that is inherently prone to error. Moreover, for workload analysis engineers to leverage existing tools against new types of analysis, it is necessary for the engineers to understand the source code and the structure of the existing tools in order to expand the tools to different applications. And, since these existing tools are typically architecture or simulator specific and complex, most engineers chose to develop new tools rather than extend existing tools, which results in duplication of work and correspondingly slowed analysis feedback.
In view of the forgoing, there is a need for providing an infrastructure for enabling software engineers and hardware engineers to gain insight into the behavior of software applications on future hardware platforms prior to the actual fabrication of hardware platforms, thereby reducing the need to extrapolate software performance characteristics from existing hardware product generations to products that are yet to be developed.